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D-Wave Announces New Hardware, Compiler, and Plans For Quantum Computing

Wednesday October 6, 2021. 03:00 PM , from Slashdot
On Tuesday, D-Wave released its roadmap for upcoming processors and software for its quantum annealers. The company is also announcing that it's going to be developing its own gate-based hardware, which it will offer in parallel with the quantum annealer. Ars Technica's John Timmer talked with company CEO Alan Baratz to understand all the announcements. An anonymous reader shares an excerpt from the report: The simplest part of the announcement to understand is what's happening with D-Wave's quantum-annealing processor. The current processor, called Advantage, has 5,000 qubits and 40,000 connections among them. These connections play a major role in the chip's performance as, if a direct connection between two qubits can't be established, others have to be used to act as a bridge, resulting in a lower effective qubit count. Starting this week, users of D-Wave's cloud service will have access to an updated version of Advantage. The qubit and connection stats will remain the same, but the device will be less influenced by noise in the system (in technical terms, its qubits will maintain their coherence longer). Further out in the future is the follow-on system, Advantage 2, which is expected late next year or the year after. This will see another boost to the qubit count, going up to somewhere above 7,000. But the connectivity would go up considerably as well, with D-Wave targeting 20 connections per qubit.

D-Wave provides a set of developer tools it calls Ocean. In previous iterations, Ocean has allowed people to step back from directly controlling the hardware; instead, if a problem could be expressed as a quadratic unconstrained binary optimization (QUBO), Ocean could produce the commands needed to handle all the hardware configuration and run the problem on the optimizer. D-Wave referred to this as a hybrid problem solver, since Ocean would use classical computing to optimize the QUBO prior to execution. The only problem is that not everyone who might be interested in trying D-Wave hardware knows how to express their problem as a QUBO. So, the new version of Ocean will allow an additional layer of abstraction by allowing problems to be sent to the system in the format typically used by people who tend to solve these sorts of problems. 'You will now be able to specify problems in the language that data scientists and data analysts understand,' Baratz promised.

The biggest part of today's announcement, however, may be that D-Wave intends to also build gate-based hardware. Baratz explained that he thinks that optimization is likely to remain a valid approach, pointing to a draft publication that shows that structuring some optimization problems for gate-based hardware may be so computationally expensive that it would offset any gains the quantum hardware could provide. But it's also clear that gate-based hardware can solve an array of problems that a quantum annealer can't. He also argued that D-Wave has solved a number of problems that are currently limiting advances in gate-based hardware that uses electronic qubits called transmons. These include the amount and size of the hardware that's needed to send control signals to the qubits and the ability to pack qubits in densely enough so that they're easy to connect but not close enough that they start to interfere with each other. One of the problems D-Wave faces, however, is that the qubits it uses for its annealer aren't useful for gate-based systems. While they're based on the same bit of hardware (the Josephson junction), the annealer's qubits can only be set as up or down. A gate-based qubit needs to allow manipulations in three dimensions. So, the company is going to try building flux qubits, which also rely on Josephson junctions but use them in a different way. So, at least some of the company's engineering expertise should still apply.

Read more of this story at Slashdot.
rss.slashdot.org/~r/Slashdot/slashdot/~3/hPfZqL8dxxo/d-wave-announces-new-hardware-compiler-and-plan...
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