IBM: Chip Making is Hitting Its Limits, But Our Techniques Could Solve That

IBM has devised materials and processes that could help improve the efficiency of chip production at the 7nm node and beyond. From a report: The company's researchers are working on challenges in the emerging field of 'area-selective deposition', a technology that could help overcome limitations on lithographic techniques to create patterns on silicon in 7nm processes. Semi Engineering has a neat account of lithographic patterning and why at 7nm there's growing interest in area-selective deposition. Techniques such as 'multiple patterning' helped ensure integrated circuits kept scaling, but as chips have shrunk from 28nm to 7nm processes, chipmakers have needed to process more layers with ever-smaller features that need more precise placement on patterns. Those features need to align between layers. When they don't, it leads to 'edge placement error' (EPE), a challenge that Intel lithography expert Yan Borodovsky believed lithography couldn't solve and which would ultimately impede Moore's Law.

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